{"title":"Dual latency operation in VDSL2 with downstream power back off","authors":"S. Ravishankar, Padmaja, S. Sridhar","doi":"10.1109/TENCON.2008.4766433","DOIUrl":null,"url":null,"abstract":"The main advantage of down stream power back off (DPBO) in VDSL2 is coexistence with ADSL. The ADSL link bit error rate (BER) will not get affected by introducing VDSL2 in the same binder. In this paper we present a new scheme that partitions the tones over the two latency paths based on signal-to-noise (SNR) with DPBO included in the computation. The bit loading is done from the obtained SNR profile using the standard rate adaptive water filling algorithm. The data rate of the VDSL2 system is calculated by realigning the tone loading after accounting for the fractional bits. Simulation results include bit loading pattern and data rates for the two paths with DPBO. It is further implemented on the TMS DSP processor 6713 and results hence obtained are found to match with the simulation results.","PeriodicalId":22230,"journal":{"name":"TENCON 2008 - 2008 IEEE Region 10 Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"TENCON 2008 - 2008 IEEE Region 10 Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.2008.4766433","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The main advantage of down stream power back off (DPBO) in VDSL2 is coexistence with ADSL. The ADSL link bit error rate (BER) will not get affected by introducing VDSL2 in the same binder. In this paper we present a new scheme that partitions the tones over the two latency paths based on signal-to-noise (SNR) with DPBO included in the computation. The bit loading is done from the obtained SNR profile using the standard rate adaptive water filling algorithm. The data rate of the VDSL2 system is calculated by realigning the tone loading after accounting for the fractional bits. Simulation results include bit loading pattern and data rates for the two paths with DPBO. It is further implemented on the TMS DSP processor 6713 and results hence obtained are found to match with the simulation results.