A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system

Shunli Ma, Guangyao Zhou, Jia-Feng Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
{"title":"A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system","authors":"Shunli Ma, Guangyao Zhou, Jia-Feng Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren","doi":"10.1109/ESSCIRC.2015.7313847","DOIUrl":null,"url":null,"abstract":"This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.
用于22 ~ 31.4 GS/s实时采样系统的校准正交时钟发生器
提出了一种用于超高速实时采样系统的带相位标定的精确正交时钟信号。所提出的四相时钟发生器是一个锁相环(PLL),具有一种新颖的正交分频器,可以实现可调的正交相位来校准可变失配。所提出的正交时钟的工作频率可以在5.5GHz到7.85GHz之间进行调谐,可用于四通道时间交错采样器。实时采样系统实现28-31.2GS/s的采样率。芯片功耗为28mW,电源电压为1.2V,采用台积电65nm CMOS工艺。测量结果表明,校准相位可以覆盖±10°的I相与Q相失配。相位噪声为-115 dBc/Hz@1MHz,中心频率为6.85GHz,周期间时间RMS抖动为210fs。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信