TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

Abstract

TCAD simulations have been performed to optimize well designed planar single-gate silicon (Si) vertical tunneling junction field effect transistor (VTFET) with average subthreshold swing (S.S.) less than 60 mV/dec for 0.3 V (=Vgs=Vds) operation. By scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length Lov, it achieved both on-current (Ion) greater than 1.0 A/m and low average S.S. without pocket doping for forming tunnel junction in conventional VTFET.