{"title":"A 50–110 GHz Four-Channel Dual Injection Locked Power Amplifier with 36% PAE at 19 dBm Psat Using Self-Start Technique in 65 nm CMOS Process","authors":"Shunli Ma, Fan Ye, Junyan Ren","doi":"10.1109/MWSYM.2018.8439345","DOIUrl":null,"url":null,"abstract":"This brief presents a wideband and high power-added efficiency (PAE) mm-wave injection-locked power amplifier (ILPA). It consists of four channels and each channels has four stages including input buffer, dual injection-locked stages and output driver stage. Due to the proposed dual injection-locked stages, the PA overcomes the narrow bandwidth drawbacks of conventional ILPAs and realize high energy efficiency. The testing chip was fabricated in 65 nm CMOS process in an area of 0.6 mm2, The PA supply voltage is 1 V with the dc power consumption of 91 mW. Measured results show the presented PA achieves bandwidth of 50–110 GHz with a small-signal gain of 20 dB. The 1-dB output power value is 19 dBm with 36% Dower-added efficiency (PAE).","PeriodicalId":6675,"journal":{"name":"2018 IEEE/MTT-S International Microwave Symposium - IMS","volume":"33 1","pages":"1449-1452"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE/MTT-S International Microwave Symposium - IMS","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2018.8439345","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This brief presents a wideband and high power-added efficiency (PAE) mm-wave injection-locked power amplifier (ILPA). It consists of four channels and each channels has four stages including input buffer, dual injection-locked stages and output driver stage. Due to the proposed dual injection-locked stages, the PA overcomes the narrow bandwidth drawbacks of conventional ILPAs and realize high energy efficiency. The testing chip was fabricated in 65 nm CMOS process in an area of 0.6 mm2, The PA supply voltage is 1 V with the dc power consumption of 91 mW. Measured results show the presented PA achieves bandwidth of 50–110 GHz with a small-signal gain of 20 dB. The 1-dB output power value is 19 dBm with 36% Dower-added efficiency (PAE).