RDL Copper Plating Process for Panel Level Packaging Application

Maddux Sy, Sean Fleuriel, Confesol Rodriguez, Kesheng Feng, Robert Moon, Dolores Cruz, J. Hander
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Abstract

Advanced packaging suppliers are having two primary challenges during IC substrate fabrication, meeting the requirements on copper plating performance and reducing the cost from manufacturing process. The requirements on plating performance include high resolution and strict height uniformity within a die (WID) and within a panel (WIP), consistent deposit grain structure, and robust physical properties to meet reliability requirements. The plated features include fine lines, trenches, and vias, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, without any special post treatment are highly desirable features from RDL plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single electrolyte, this flexibility allows fabricators to save on space and equipmentIn this paper, an electroplating package, Systek UVF 200, is introduced to plate RDL under different current densities in vertical continuous platers (VCP) and a high-speed panel plater. The plating uniformity was evaluated on a panel level in a high-speed plater, AMSPT NEXX P500.The Systek UVF 200 package offered excellent coplanarity within a pattern unit or die for RDL plating. The variation in the plated height (or thickness) between fine lines (as low as 9 μm in width) and pads, was below 2.0 μm when using a current density below 5.0 ASD to obtain the plated copper thickness around 12 μm. For 14 μm wide lines, the plated copper thickness variation can be below 1.2 μm. The variation of plated thickness across 510 mm x 515 mm panels was below 5%. The tops of the fine lines have defined, slightly domed shapes, these types of profiles have excellent conductivity.Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit to withstand thermal stress and warpage. The additives (wetter, brightener, and leveler) strongly influence the physical properties of the deposit. Copper deposited with the Systek UVF 200 package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change under different current density, showing that the package has stable performance.
面板级封装用RDL镀铜工艺
先进封装供应商在IC基板制造过程中面临着两个主要挑战,即满足镀铜性能的要求和降低制造过程中的成本。对电镀性能的要求包括高分辨率和严格的模具内(WID)和面板内(WIP)高度均匀性,一致的沉积颗粒结构,以及满足可靠性要求的坚固的物理性能。镀的特征包括细线,沟槽和通孔,其顶部形状和共平面度对产品质量至关重要。非平面表面可能导致信号传输损失,并在连接中引入弱点。因此,提供均匀的平面结构的镀铜溶液,无需任何特殊的后处理,是RDL镀工艺非常理想的特征。镀铜解决方案还可以通过在单一电解质中镀两种或三种类型的特征来降低成本,这种灵活性使制造商节省了空间和设备。在本文中,介绍了一种电镀封装系统UVF 200,用于在垂直连续镀板(VCP)和高速面板镀板中在不同电流密度下镀RDL。在高速镀板AMSPT NEXX P500的面板水平上评估镀层均匀性。systemk UVF 200封装在RDL电镀的图案单元或模具内提供了出色的共平面性。当电流密度低于5.0 ASD,镀铜厚度约为12 μm时,细线(低至9 μm)与焊盘之间的镀高(或厚度)变化小于2.0 μm。对于14 μm宽的线,镀铜厚度变化可小于1.2 μm。在510毫米x 515毫米面板上镀厚度的变化小于5%。细线的顶部有明确的,略带圆顶的形状,这些类型的型材具有优异的导电性。镀铜镀层的物理性能对成品的可靠性至关重要。一些关键的物理性能是抗拉强度、伸长率和内应力。这些特性显示了沉积层对热应力和翘曲的耐受性。添加剂(润湿剂、增白剂和匀平剂)对镀层的物理性质有很大影响。采用systemk UVF 200封装的铜的抗拉强度超过40000 psi,伸长率超过18%,内应力低于1.0 Kg/mm2。在不同的电流密度下,沉积铜的物理性质没有发生变化,表明该封装具有稳定的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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