Impact of Analog Memories Non-Idealities on the Performance of Foreground Detection Algorithms

Abstract

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.