Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience

E. You, S. Choe, Chin-Man Kim, L. Varadadesikan, K. Aingaran, J. MacDonald
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引用次数: 5

Abstract

This paper discusses accuracy issues in parasitic extraction for the design of multimillion-transistor integrated circuits. The methodology reported aims at reducing the gap between the parasitic values estimated during implementation and the results of post-layout extraction. The objective is to obtain progressively refined interconnect models in hierarchical design flows. This methodology was developed for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.
百万晶体管集成电路的寄生提取:方法和设计经验
本文讨论了百万晶体管集成电路设计中寄生提取的精度问题。所报告的方法旨在减少在实施过程中估计的寄生值与布局后提取结果之间的差距。目标是在分层设计流程中获得逐步细化的互连模型。该方法是为800 MHz UltraSPARC-III微处理器开发的。我们的实验结果证明了提取方法对互连建模以及随后的时序和噪声分析的深远影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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