Design of an All-digital Time Domain Analog-to-digital Converter Based on Ring Delay Line Technology

Abstract

A novel voltage-to-time converter (VTC) with high linearity and wide dynamic input range is used for low-power time-domain ADC in this paper, which combines the advantages of body bias technique and current mirror technique. The proposed time-domain ADC (T-ADC) consists of ring delay line, counter, encoder and subtractor. The time-domain ADC is implemented based on the XFAB 0.18μm COMS standard process, and the overall power consumption is 37.7μW under a 1.8V supply voltage. The simulated ENOB, SNDR, and SFDR are 10.72-bits, 66.31dB, and 76.13dB respectively at the Nyquist frequency.