A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard

Abstract

The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm2 and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.