A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration

Abstract

This paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V.