A scalable processing-in-memory accelerator for parallel graph processing

Junwhan Ahn, Sungpack Hong, S. Yoo, O. Mutlu, Kiyoung Choi
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引用次数: 722

Abstract

The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.
用于并行图形处理的可扩展内存处理加速器
数字数据的爆炸式增长和对快速数据分析的日益增长的需求使得内存大数据处理在计算机系统中变得越来越重要。特别是大规模图处理由于其从社会科学到机器学习的广泛适用性而受到关注。然而,能够在主存中有效处理大型图形的可扩展硬件设计仍然是一个开放的问题。理想情况下,成本效益和可扩展的图形处理系统可以通过构建一个系统来实现,该系统的性能与系统中可以存储的图形大小成比例地增加,这在传统系统中由于严重的内存带宽限制而极具挑战性。在这项工作中,我们认为内存中处理(PIM)的传统概念可以成为实现这一目标的可行解决方案。PIM的关键现代推动者是3D集成技术的最新进展,该技术有助于将逻辑和存储芯片堆叠在单个封装中,这在最初研究PIM概念时是不可用的。为了利用这种新技术来实现内存容量比例性能,我们设计了一个可编程的PIM加速器,用于大规模图形处理,称为Tesseract。Tesseract由(1)充分利用可用内存带宽的新硬件架构,(2)不同内存分区之间有效的通信方法,以及(3)反映和利用独特硬件设计的编程接口组成。它还包括两个专门用于图形处理的内存访问模式的硬件预取器,它们基于我们的编程模型提供的提示进行操作。我们使用五种最先进的图形处理工作负载和大型真实世界图形进行综合评估,结果表明,所提出的架构将平均系统性能提高了十倍,并且比传统系统平均节能87%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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