A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS

Abstract

Given the continuously climbing data rates of high-speed I/O's, equalizer circuits-and particularly decision-feedback equalizer (DFE) designs-are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates, loop-unrolled DFEs are widely adopted to relieve the feedback timing constraints of the initial tap(s) [1]. However, loop-unrolling introduces additional delay into the critical paths of later (non-unrolled) DFE taps due to the selection MUXes, and with its exponential growth in complexity, does not scale well as the number of unrolled taps increases. Perhaps due to this challenge, no multi-tap DFE solutions with single pJ/bit efficiencies have yet been demonstrated at data rates >40Gb/s.