Design and Implementation of SORIGA-optimized Powers-of-two FIR Filter on FPGA

Abhijit Chandra , Sudipta Chattopadhyay , Beetan Ghosh
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引用次数: 4

Abstract

With the introduction of sophisticated algorithms, the field of signal processing has experienced enormous diversification of late. In addition to this, design of hardware efficient digital systems has grown sufficient interest amongst the researchers in recent past. In this article, an attempt has been made to realize hardware friendly powers-of-two FIR filter by using an evolutionary computation, called Self-organizing Random Immigrants Genetic Algorithm (SORIGA). In connection to this, this work makes one comparative study amongst various multiplier-less FIR filters in terms of hardware complexity when implemented on an FPGA chip. Finally, supremacy of the proposed design has firmly been established by comparing its hardware cost with many of the state-of-the-art powers-of-two FIR filters.

soriga优化的2倍功率FIR滤波器在FPGA上的设计与实现
近年来,随着复杂算法的引入,信号处理领域经历了巨大的多样化。除此之外,硬件高效数字系统的设计近年来也引起了研究人员的极大兴趣。在本文中,我们尝试使用一种称为自组织随机移民遗传算法(SORIGA)的进化计算来实现硬件友好的2次幂FIR滤波器。与此相关,本研究在FPGA芯片上实现的各种无乘法器FIR滤波器的硬件复杂性方面进行了比较研究。最后,通过将其硬件成本与许多最先进的两倍功率FIR滤波器进行比较,确定了所提出设计的优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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