A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573555

Wei Tang, Chia-Hsiang Chen, Zhengya Zhang

引用次数: 19

Abstract

A 0.58mm2 40nm CMOS message-passing detector (MPD) is designed for a 256-QAM massive MIMO system supporting 32 concurrent mobile users in each time-frequency resource. Leveraging channel hardening in massive MIMO, a symbol hardening technique is proposed to reduce MPD's complexity by more than 60% with minimal SNR loss. The MPD is implemented in a 4-layer 2-way interleaved architecture to enable a 2.76Gb/s throughput (average 4.9 iterations at 27dB SNR with early termination) using 76% smaller area than a fully parallel architecture. With dynamic precision control and clock gating to exploit algorithmic properties, the energy is reduced to 79.8pJ/b (or 2.49pJ/b per TX antenna).

查看原文本刊更多论文

一个0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM大规模MIMO消息传递检测器

设计了一种0.58mm2 40nm CMOS消息传递检测器(MPD)，用于256-QAM大规模MIMO系统，每个时频资源支持32个并发移动用户。利用大规模MIMO中的信道强化，提出了一种符号强化技术，以最小的信噪比损失将MPD的复杂性降低60%以上。MPD采用4层双向交错架构，吞吐量为2.76Gb/s(平均4.9次迭代，信噪比为27dB，提前终止)，面积比完全并行架构小76%。通过动态精确控制和时钟门控来利用算法特性，能量降低到79.8pJ/b(或每个TX天线2.49pJ/b)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

自引率

0.00%

发文量