Through the Concurrency Gateway: a Challenge from the Near Future of Graphics Hardware

P. Welch
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Abstract

The computer graphics industry, and in particular those involved with films, games and virtual reality, continue to demand more and more realistic computer generated images. The complexity of the scenes being modelled and the high fidelity required of the images means that rendering is simply not possible in a reasonable time (let alone real-time) on a single computer[BrW03]. Interactive ray tracing exists today[WSB*01], but real-time global illumination remains a major challenge. Fortunately, "computer graphics cards are developing at Moore's law cubed" [David Kirk, Chief Scientist, nVIDIA]. Such performance increases are directly due to the inherent parallel nature of modern graphics cards. If this trend continues, they will be 100 times faster in a mere 3.5 years time, 1000 times faster in 5 years and they will be massively parallel. Unfortunately, past experiences in designing systems that can exploit parallel processors in anything beyond embarrassingly trivial ways are not encouraging. For real-time interaction with high fidelity images, the parallel processing requirements will not be embarrassingly trivial! Regular and irregular patterns of synchronisation and communication will have to be managed over networks of fine-grained (for accuracy) model components whose scale, topology and physical distribution are dynamically evolving. This paper reviews weaknesses in our standard approaches to the design and implementation of concurrent systems and describes ways forward that are mature and practical - both for the programmer to program and the hardware to execute. They are built on decades of research into process algebrae (CSP and the p-calculus), but are able to preserve and exploit traditional skills and capabilities of serial software engineering and von Neumann architecture (components of which will still form the processor base of parallel systems for at least the next decade). The changes are, therefore, evolutionary rather than revolutionary - but are nevertheless essential both in the field of graphics and for the wider Grand Challenges of computer science.
通过并发网关:来自近期图形硬件的挑战
计算机图形工业,特别是那些涉及电影、游戏和虚拟现实的行业,继续要求越来越多的逼真的计算机生成图像。被建模的场景的复杂性和图像所需的高保真度意味着渲染根本不可能在一个合理的时间(更不用说实时)在一台计算机上[BrW03]。交互式光线追踪已经存在[WSB*01],但实时全局照明仍然是一个主要挑战。幸运的是,“计算机图形卡正在按照摩尔定律的立方发展”[David Kirk, nVIDIA首席科学家]。这种性能的提高直接归功于现代显卡固有的并行特性。如果这种趋势继续下去,它们将在3.5年的时间内快100倍,在5年内快1000倍,它们将大规模并行。不幸的是,在设计系统时,除了以令人尴尬的琐碎方式利用并行处理器之外,以往的经验并不令人鼓舞。对于与高保真图像的实时交互,并行处理的要求将不会小得令人尴尬!规则和不规则的同步和通信模式必须在细粒度(为了准确)模型组件的网络上进行管理,这些组件的规模、拓扑和物理分布是动态发展的。本文回顾了我们设计和实现并发系统的标准方法中的弱点,并描述了成熟和实用的方法-无论是程序员编程还是硬件执行。它们建立在对过程代数(CSP和p-微积分)几十年的研究基础上,但能够保留和利用串行软件工程和冯·诺伊曼体系结构的传统技能和能力(其组件至少在未来十年仍将构成并行系统的处理器基础)。因此,这些变化是渐进式的,而不是革命性的,但无论在图形领域还是在更广泛的计算机科学大挑战中,它们都是必不可少的。
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