xB+-Tree: Access-Pattern-Aware Cache-Line-Based Tree for Non-volatile Main Memory Architecture

Abstract

Non-volatile memory (NVM) has widely participated in the evolution of the next-generation memory architecture by way of being the substitution of the main memory. To cope with the problem of asymmetric read/write speeds of NVM, several excellent researches have been proposed to reduce the number of writes to the NVM-based main memory. Nevertheless, most of these existing approaches do not take the cache-line-based access behavior between the processor and the main memory into consideration. Thus, in order to essentially improve the access performance of the NVM-based memory architecture, this work aims to optimize the cache-line-based access performance over the NVM-based memory architecture based on the special access patterns in many popular internet of things (IoT) and in-memory database applications. Our experiments based on the well-known Gem5 full system simulator reveal that, compared to other existing representative approaches, the proposed design can effectively reduce the total execution time of insertion by 20.92~55.20% and improve the execution time of query by 2.06~23.36%.