A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

K. Uyttenhove, A. Marques, M. Steyaert
{"title":"A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction","authors":"K. Uyttenhove, A. Marques, M. Steyaert","doi":"10.1109/CICC.2000.852659","DOIUrl":null,"url":null,"abstract":"In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"54","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 54

Abstract

In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.
具有数字纠错功能的6位1 GHz采集速度CMOS闪存ADC
本文介绍了一种最大采集速度为1ghz的6位CMOS模数转换器(a /D)。由于元稳定性问题降低了高采样频率下的无杂散动态范围(SFDR),因此在该设计中需要特别注意。测量的SNDR(信噪比加失真)在500 MHz时钟和f/sub /=141 kHz时超过30 dB。在250 MHz以下的输入频率下,测量到的SFDR大于30 dB。该芯片采用标准的0.35 /spl mu/m双聚CMOS工艺加工,占据0.8 mm/sup /的有效面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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