Recent Advances in Underfill for New Package Architectures

Abstract

Various types of advanced packages are available, including Fan-Out Wafer Level Package (FO-WLP), Flip-Chip Chip-Scale Package (FC-CSP) and Flip-Chip Ball Grid Arrays (FC-BGA) packages. These advanced packages are migrating to multi-chip package architectures such as 2.3D, 2.5D technology [1]–[6]. These advanced ball grid arrays (BGAs) incorporate multiple dies on a substrate or an interposer. This paper examines the motivation for the move toward heterogeneous integration of multi-chip architecture by a comparison of die size and die yield. It also reports the results of the 2.5D package trend analysis. By comparing a silicon interposer with a redistribution layer (RDL) interposer, further simulations were performed to investigate the thermomechanical stress behavior of an interposer package against the warpage of the package and tensile stress of underfill and micro-bumps [7]. For a multi-die interposer package, underfill seals below and between the die areas. Between the dies, the underfill was sealed vertically like a wall. The stress distribution of the underfill between the die and the interposer, the underfill between the interposer and the substrate, and the vertical underfill wall is discussed. Low Coefficient-of-Thermal-Expansion (CTE)/high modulus underfill was compared to high CTE/low modulus underfill in the same interposer package.