{"title":"Threshold Detection ADC For Continuous Monitoring Applications","authors":"Annamaria Fordymacka, I. O'Connell","doi":"10.1109/MWSCAS47672.2021.9531751","DOIUrl":null,"url":null,"abstract":"The proposed threshold detection based ADC targets continuous monitoring systems, where full reconstruction of the input signal isn’t required. The ADC observes whether the input signal stays within safety margins keeping the microcontroller in the standby mode until alarm occurs. This approach generates significantly less output data that needs to be wirelessly transmitted, thereby resulting in significant power savings in the system. This proposed ADC takes full advantage of a ∆Σ DAC allowing for high flexibility and requiring only one decision clock cycle independent of the target resolution. This compact design occupies only 0.012 mm2 in 65 nm CMOS with 10 bits resolution.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"19 1","pages":"571-574"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531751","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The proposed threshold detection based ADC targets continuous monitoring systems, where full reconstruction of the input signal isn’t required. The ADC observes whether the input signal stays within safety margins keeping the microcontroller in the standby mode until alarm occurs. This approach generates significantly less output data that needs to be wirelessly transmitted, thereby resulting in significant power savings in the system. This proposed ADC takes full advantage of a ∆Σ DAC allowing for high flexibility and requiring only one decision clock cycle independent of the target resolution. This compact design occupies only 0.012 mm2 in 65 nm CMOS with 10 bits resolution.