Pre-placement evaluation of Standard Cell Library compliance to Process Density constraints

Abstract

Improving design manufacturability and yield requires microchip designs to satisfy process density constraints for pre-defined windows in the die. Iterations in DFM convergence poses a key challenge to physical verification which heavily depends on the compliance of standard cell library to process density requirements. The proposed novel technique involves training a classifier model using supervised reinforced learning to evaluate layer wise density margin as a function of cell area, process window overlaps and usage at block-level thus facilitating ease of use. Process density compliance is analyzed for library offerings on Intel 10nm node demonstrating 85% success in predicting failing cells