Hirotaka Murakami, E. Bohannon, J. Childs, Grace Gui, E. Moule, Katsuhiko Hanzawa, Tomofumi Koda, Chiaki Takano, T. Shimizu, Yuki Takizawa, Adarsh Basavalingappa, R. Childs, Cody R. Cziesler, R. Jarnot, Kazumasa Nishimura, S. Rogerson, Y. Nitta
{"title":"A 4.9Mpixel Programmable-Resolution Multi-Purpose CMOS Image Sensor for Computer Vision","authors":"Hirotaka Murakami, E. Bohannon, J. Childs, Grace Gui, E. Moule, Katsuhiko Hanzawa, Tomofumi Koda, Chiaki Takano, T. Shimizu, Yuki Takizawa, Adarsh Basavalingappa, R. Childs, Cody R. Cziesler, R. Jarnot, Kazumasa Nishimura, S. Rogerson, Y. Nitta","doi":"10.1109/ISSCC42614.2022.9731607","DOIUrl":null,"url":null,"abstract":"Today's mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a $2560(\\mathsf{H})\\times 1920(\\mathsf{V})$ pixel array that, at 1fps, consumes $790\\mu\\mathsf{W}$ for full-color VGA and 120µW for motion-detection (MD) mode.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"190 1","pages":"104-106"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42614.2022.9731607","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Today's mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a $2560(\mathsf{H})\times 1920(\mathsf{V})$ pixel array that, at 1fps, consumes $790\mu\mathsf{W}$ for full-color VGA and 120µW for motion-detection (MD) mode.