A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines

Abstract

This paper presents the highest measured read access frequency for a multi-ported register file (RF) fabricated in a low-power (LP) 1.2V TSMC 65nm low-Vt CMOS process. Active power is reduced with the use of low-capacitance dynamic local bitlines (LBLs). The dc noise robustness of low-Vt dynamic LBLs is enhanced by 94% compared to conventional low-Vt dynamic LBLs with novel gated inverter-based read port architecture. The 2-read, 1-write-ported 32-entry × 32-bit per word RF demonstrates measured 3.2GHz operation at 1.2V by consuming 44.2mW of active power and 197.5μW of leakage power. The RF is measured down to 0.4V.