A 350mV–900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS

Abstract

A regular expression matching on-die accelerator, consisting of a hybrid deterministic finite automata (HDFA) and Bloom filter (BLM), with measured 2.1GHz operation, is fabricated in 14nm tri-gate CMOS and occupies 0.011mm2. HDFA integrates probability-based truncation, unique transition-state pairs isolation, parallel common transitions detection, and NFA empty transitions. BLM implements a fused 2-hash NOR match bit-line, 1bit read circuits, and sparse H3 hash. These techniques and aging-tolerant read/write register file circuits (120mV/180mV improved VMIN) achieve 350mV-900mV wide dynamic voltage range with peak throughput of 15.2Gbps-17.1Gbps consuming 3.7mW-4.5mW measured at 750mV, 25°C and maximum energy-efficiency of 17.5Tbps/W-12.5Tbps/W measured at near-threshold 350mV.