Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI:10.1109/ISSCC42614.2022.9731678

T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar

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引用次数: 11

Abstract

“Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex unit (CCX) consists of 8 “Zen 3” cores, each with a 0.5MB private L2 cache, and a 32MB shared L3 cache. Increasing this from 4 cores and 16MB L3 in the prior generation provides additional performance uplift, in addition to the IPC and frequency improvements. The “Zen 3” CCX shown in Fig. 2.7.1 contains 4.08B transistors in 68mm2, and is used across a broad array of client, server, and embedded market segments.

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Zen3: AMD第二代7nm x86-64微处理器核心

“Zen 3”是AMD Zen系列微处理器中第一个主要的微架构重新设计。考虑到与上一代“Zen 2”核心相同的7nm工艺技术[1]，以及相同的平台基础设施，“Zen 3”的主要设计目标是提供:1)显著提升每周期指令数(IPC)， 2)大幅提升频率，以及3)持续改进功率效率。核心复杂单元(CCX)由8个“Zen 3”核心组成，每个核心都有一个0.5MB的私有L2缓存和一个32MB的共享L3缓存。从上一代的4核和16MB L3增加到IPC和频率改进，提供了额外的性能提升。图2.7.1所示的“Zen 3”CCX在68mm2中包含4.08B个晶体管，广泛用于客户端、服务器和嵌入式细分市场。

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2022 IEEE International Solid- State Circuits Conference (ISSCC)

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