Session 2: Architectures for image processing

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2016-10-01 DOI:10.1109/DASIP.2016.7853794

F. Palumbo

{"title":"Session 2: Architectures for image processing","authors":"F. Palumbo","doi":"10.1109/DASIP.2016.7853794","DOIUrl":null,"url":null,"abstract":"In the field of Signal Processing in general, and in particular in the Image Processing one, it is quite common to customize the underling architecture to improve computing efficiency. This section is dedicated to Architectures for Image Processing and four different papers will be presented. Solutions based on application specific processors, characterized on the processing requirements, may improve on board processing and facilitate data transmission from distributed computing nodes as presented in first paper. Memory hierarchy implementation and management is fundamental to improve computing efficiency. In this sense, the second paper investigates the usage of associative memories for pattern detection purposes and will apply them in the context of Clustered Neural Networks, while the third one presents a memory efficient architecture implementing in hardware the Multi-Scale Line Detector algorithm for real-time retinal blood vessel detection. Finally, the last paper is more system oriented, being focused on modelling techniques to derive and verify lossless compression IP cores.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"42"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DASIP.2016.7853794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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Abstract

In the field of Signal Processing in general, and in particular in the Image Processing one, it is quite common to customize the underling architecture to improve computing efficiency. This section is dedicated to Architectures for Image Processing and four different papers will be presented. Solutions based on application specific processors, characterized on the processing requirements, may improve on board processing and facilitate data transmission from distributed computing nodes as presented in first paper. Memory hierarchy implementation and management is fundamental to improve computing efficiency. In this sense, the second paper investigates the usage of associative memories for pattern detection purposes and will apply them in the context of Clustered Neural Networks, while the third one presents a memory efficient architecture implementing in hardware the Multi-Scale Line Detector algorithm for real-time retinal blood vessel detection. Finally, the last paper is more system oriented, being focused on modelling techniques to derive and verify lossless compression IP cores.

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第二部分:图像处理体系结构

在一般的信号处理领域，特别是图像处理领域，定制底层架构以提高计算效率是非常普遍的。本节专门介绍图像处理的体系结构，并将介绍四篇不同的论文。基于特定应用处理器的解决方案，以处理需求为特征，可以改善板上处理，并促进第一篇论文中提出的分布式计算节点的数据传输。内存层次结构的实现和管理是提高计算效率的基础。在这个意义上，第二篇论文研究了联想记忆用于模式检测的用途，并将它们应用于聚类神经网络的背景下，而第三篇论文提出了一种内存高效的架构，在硬件上实现了用于实时视网膜血管检测的多尺度线检测器算法。最后，最后一篇论文更面向系统，专注于建模技术来推导和验证无损压缩IP核。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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