Systolic processor array for radar and communications

Raymond J. Lackey, Herbert F. Baurle, John P. Barile
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引用次数: 0

Abstract

A systolic processor applicable to a general class of signal processing problems was built using commercially available VLSI floating-point processors. This processor performed over 1.25 BFLOPS (billion floating-point operations per second) in applications of solutions to a group of simultaneous equations with 12 unknowns. The solution was designed to work with the normal equations used in signal processing problems where all equations have noisy component values. The processor design was a direct implementation of algorithm mathematics in hardware and achieved a high processing rate through extensive concurrency. This program demonstrated how a custom, application-specific processor can be developed in less than two years to perform a computationally intensive function.<>
用于雷达和通信的收缩处理器阵列
利用市售的VLSI浮点处理器构建了一个适用于一般类型信号处理问题的收缩处理器。该处理器在解决一组12个未知数的联立方程的应用中执行超过1.25 BFLOPS(每秒十亿次浮点运算)。该解决方案设计用于信号处理问题中使用的正常方程,其中所有方程都具有噪声分量值。处理器设计是算法数学在硬件上的直接实现,通过广泛的并发性实现高处理率。这个程序演示了如何在不到两年的时间内开发一个定制的、特定于应用程序的处理器来执行计算密集型功能
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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