A 30 GSample/s InP/CMOS sample-hold amplifier with active droop correction

Abstract

We report a 30 GS/s sample-hold amplifier implemented in a combined InP HBT and Si CMOS heterogeneous integration technology. The high-speed signal path is entirely in InP, but droop in the sampled voltage arising from HBT bias currents is suppressed by an integrated CMOS feedback circuit. Under this closed-loop control, in hold mode, the droop rate of the single-ended outputs is reduced to 20 mV/ns. InP-CMOS interconnect parasitics are isolated from the high-speed signal path by isolation resistors and active bootstrapping. Given an 8 GHz input sampled at 32 GHz, the circuit shows input-referred P1dB and IIP3 of 0.5 dBm and 5.8 dBm, respectively. The total power consumption is 2.7 W and the chip area is 815 × 855 μm2.