An On-Chip Bus modeling and parameter simulation method based on utilization analysis

Abstract

It is necessary to estimate the system parameters such as bus utilization and buffer capacity In SoC architecture design. With the increase of complexity of system structure and communication protocol, the estimation becomes harder. The cycle-accurate modeling and simulation for the structure and data stream of On-Chip Bus is an efficient method to obtain the estimate value of above parameters. In this paper, this method is implemented by analyzing a Wishbone bus used in a Video Format Conversion chip, using Simulink. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method are verified. This method is suitable for analyzing various interconnecting architectures such as user-defined bus, industrial standard bus, multi-core and multi-bus system.