Power-delay product minimization in high-performance fixed-width multiplier

Abstract

In this paper, we propose a parallel fixed-width multiplier design that receive two n-bit numbers and produce a n-bit product. To design the proposed fixed-width multiplier, three multiplication modules are used that can work as independent smaller-precision multiplications. In order to add the outputs of the multiplication modules, carry save adder and Brent-Kung adder is used which can further improve the performance of the design. Implementation results demonstrate that the proposed fixed-width multiplier with parallel multiplication modules achieve significant improvement in delay and power-delay product when compared with previous architectures.