{"title":"Fault-tolerance of reconfigurable logic in memory using AGT","authors":"C. Subashini, T. Mohanapriya, U. Rajaram","doi":"10.1109/ICICES.2014.7034177","DOIUrl":null,"url":null,"abstract":"Fault handling is an important metric for many operating environments. The traditional technique for improving reliability of system is by replicating the system component. This paper explains about the Adaptive group testing technique for isolating the faults which is present in the memory of the system. The memory element contains many cell and these cells are grouped into number of blocks. These blocks are tested. The test vectors are produced sly LFSR and this is introduced into the circuit to validate the correct working of the system. This work is incorporated into FPGA to provide an adaptive hardware system with self-isolating properties. This approach increases the performance of the system. This testing is designed using hardware description language called VHDL.","PeriodicalId":13713,"journal":{"name":"International Conference on Information Communication and Embedded Systems (ICICES2014)","volume":"22 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Information Communication and Embedded Systems (ICICES2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICES.2014.7034177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Fault handling is an important metric for many operating environments. The traditional technique for improving reliability of system is by replicating the system component. This paper explains about the Adaptive group testing technique for isolating the faults which is present in the memory of the system. The memory element contains many cell and these cells are grouped into number of blocks. These blocks are tested. The test vectors are produced sly LFSR and this is introduced into the circuit to validate the correct working of the system. This work is incorporated into FPGA to provide an adaptive hardware system with self-isolating properties. This approach increases the performance of the system. This testing is designed using hardware description language called VHDL.