FPGA partitioning and synthesis of reconfigurable video compression module

Abstract

Nowadays Field Programmable Gate Arrays (FPGAs) are increasingly considered in space applications as they are flexible and reprogrammable. They play an important role in geographical and weather forecasting processes. However, these devices are sensitive to the effects of radiation especially in modern de signs that deal with smaller CMOS structures. This paper discusses the various steps involved in designing a video compression system that can be used for space applications. A brief idea of a self-repairing algorithm is also proposed that can help in sustaining the compression system for a longer duration. The algorithm is based on modern reconfigurable architectures. The different steps involved in compression are designed using Verilog HDL. The design is simulated and synthesized using Xilinx IS E 14.2.