Design & Performance Analysis of Low Power 1-bit Full Adder at 90 nm node using PTL Logic

Abstract

This paper explores a new full-adder (FA) cell which works in low power. Here the FA architecture is designed using pass transistor logic (PTL) style with 14 transistors and implemented using Cadence Virtuous Tools in 90 nm technology node. The investigation has been carried out through anatomizing the FA cell into sub modules. The different design metrics are compared with the existing design. The result shows an average power and delay of 1.494 μW and 0.003612 ns respectively, which is less compared with the existing FA.