A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS

Abstract

Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delay-matching buffers [1] or delay calibration loops [1-2] to guarantee that timing constraints are always met at the desired bit-rate across all PVT corners. This additional circuitry increases power, area, and overall complexity of the transmitter. The timing constraint and power penalty are particularly severe when the data rate is high compared to the inherent speed of the technology.