Low power FPGA design using post-silicon device aging (abstract only)

Abstract

The impact of process variation (PV) in deep submicron CMOS technologies has raised major concerns for energy optimization efforts in FPGAs. We have developed a post-silicon leakage energy optimization scheme that raises the threshold voltage (by way of negative bias temperature instability (NBTI) aging) of the components that are either unused or not on the critical timing paths, thereby reducing the total leakage energy consumption. In order to obtain the input vectors for aging only the targeted transistors, we map the problem of minimizing leakage energy under timing constraints to an instance of the satisfiability (SAT) problem. We implemented low power designs targeting Xilinx Spartan6 FPGAs and analyzed the potential leakage power savings over a set of ITC99 and Opencores benchmarks. The analysis of the experimental results shows a substantial amount of potential leakage energy reduction with very small performance degradation.