Low power bus coding techniques considering inter-wire capacitances

Abstract

The power dissipation associated with driving data buses can be significant, especially considering the increasing component of inter-wire capacitance. Previous work on bus encoding has focused on minimizing transitions to reduce power dissipation. In this paper, it is shown that transition reduction is not necessarily the best approach for reducing power when the effects of inter-wire capacitance are considered. An electrical model for data buses designed with submicron technologies is presented and a family of coding techniques is proposed that can reduce the average power consumption of the bus by 40%.