1 Gb stacked solution of multilevel NOR flash memory packaged in a LFBGA 8 mm by 10 mm by 1.4 mm of thickness

M. Dellutri, P. Pulici, D. Guarnaccia, P. Stoppino, G. Vanalli, T. Lessio, F. Vassallo, R. Di Stefano, G. Labriola, A. Tenerello, F. Lo Iacono, G. Campardo
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引用次数: 6

Abstract

The evolution of electronic world is running toward more and more complex devices even looking for a reduction of the overall system dimensions. This improvement is particularly evident in the wireless applications where portable devices are becoming the key products. Many different applications have been inserted in the last years to satisfy all the increasing final user requirements, without affecting the final device dimensions. This important goal was possible due to many technical achievements in term of integration, the stacked package solutions being the most relevant among them. This assembly technology allows putting more dice one upon the other in a unique package so exploiting its z-dimension. This work aims to describe a multi-memory stacked device of 1 Gb size of the NOR flash memory composed by a four 256Mb dice stacked structure. This solution allows increasing the memory size maintaining the electrical performances of the multilevel NOR flash i.e. speed class. The structure is composed by seven dice: four active and three dummy interposers to create the physical space for the wires bonding from die pads to package substrate (Titus et al., 2004). The package is a LFBGA (low fine pitch ball grid array) 8 mm by 10 mm by 1.4 mm with 88 balls (0.8 mm pitch). An embedded circuitry in the die implements the logic to allow the system to be managed as a monolithic 1 Gb. Moreover, a description of the electrical analysis is reported in order to highlight the electromagnetic interferences between the different dice and the signal integrity of the whole system. Some samples of the device have been assembled in a package without molding in order to make measurements even on the pad of the devices and other critical nodes internal into the package
1gb多层NOR闪存的堆叠解决方案,封装在厚度为8mm × 10mm × 1.4 mm的LFBGA中
电子世界的发展正朝着越来越复杂的设备发展,甚至寻求减少整体系统的尺寸。这种改进在无线应用中尤其明显,便携式设备正在成为关键产品。在过去的几年中,已经插入了许多不同的应用程序,以满足所有不断增长的最终用户需求,而不影响最终设备尺寸。由于集成方面的许多技术成就,这一重要目标成为可能,堆叠封装解决方案是其中最相关的。这种组装技术允许在一个独特的封装中放置更多的骰子,从而利用其z维度。本工作旨在描述一个由4个256Mb的骰子堆叠结构组成的1gb大小的NOR闪存多存储器堆叠器件。该解决方案允许增加内存大小,保持多电平NOR闪存的电气性能,即速度等级。该结构由7个骰子组成:4个有源和3个虚拟中间体,用于为从模垫到封装基板的导线键合创造物理空间(Titus等,2004)。该封装是LFBGA(低细间距球网格阵列),8mm × 10mm × 1.4 mm, 88个球(0.8 mm间距)。芯片中的嵌入式电路实现了逻辑,允许系统作为1gb的单片管理。此外,为了突出不同骰子之间的电磁干扰和整个系统的信号完整性,报告了电分析的描述。一些样品的设备已经组装在一个包没有成型,以便进行测量,甚至在垫的设备和其他关键节点内部的封装
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