Deep analog-to-digital converter for wireless communication

Ashkan Samiee, Yiming Zhou, Tingyi Zhou, B. Jalali
{"title":"Deep analog-to-digital converter for wireless communication","authors":"Ashkan Samiee, Yiming Zhou, Tingyi Zhou, B. Jalali","doi":"10.1117/12.2576967","DOIUrl":null,"url":null,"abstract":"With the advent of the 5G wireless networks, achieving tens of gigabits per second throughputs and low, milliseconds, latency has become a reality. This level of performance will fuel numerous real-time applications, such as autonomy and augmented reality, where the computationally heavy tasks can be performed in the cloud. The increase in the bandwidth along with the use of dense constellations places a significant burden on the speed and accuracy of analog-to-digital converters (ADC). A popular approach to create wideband ADCs is utilizing multiple channels each operating at a lower speed in the time-interleaved fashion. However, an interleaved ADC comes with its own set of challenges. The parallel architecture is very sensitive to the inter-channel mismatch, timing jitter, clock skew between different ADC channels as well as the nonlinearity within individual channels. Consequently, complex post-calibration is required using digital signal processing (DSP) after the ADC. The traditional DSP calibration consumes a significant amount of power and its design requires knowledge of the source and type of errors which are becoming increasingly difficult to predict in nanometer CMOS processes. In this paper, instead of individually targeting each source of error, we utilize a deep learning algorithm to learn the complete and complex ADC behavior and to compensate for it in realtime. We demonstrate this \"Deep ADC\" technique on an 8G Sample/s 8-channel time-interleaved ADC with the QAM-OFDM modulated data. Simulation results for different QAM symbol constellations and OFDM subcarriers show dramatic improvements of approximately 5 bits in the dynamic range with a concomitant drastic reduction in symbol error rate. We further discuss the hardware implementation including latency, power consumption, memory requirements, and chip area.","PeriodicalId":8487,"journal":{"name":"arXiv: Signal Processing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv: Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2576967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

With the advent of the 5G wireless networks, achieving tens of gigabits per second throughputs and low, milliseconds, latency has become a reality. This level of performance will fuel numerous real-time applications, such as autonomy and augmented reality, where the computationally heavy tasks can be performed in the cloud. The increase in the bandwidth along with the use of dense constellations places a significant burden on the speed and accuracy of analog-to-digital converters (ADC). A popular approach to create wideband ADCs is utilizing multiple channels each operating at a lower speed in the time-interleaved fashion. However, an interleaved ADC comes with its own set of challenges. The parallel architecture is very sensitive to the inter-channel mismatch, timing jitter, clock skew between different ADC channels as well as the nonlinearity within individual channels. Consequently, complex post-calibration is required using digital signal processing (DSP) after the ADC. The traditional DSP calibration consumes a significant amount of power and its design requires knowledge of the source and type of errors which are becoming increasingly difficult to predict in nanometer CMOS processes. In this paper, instead of individually targeting each source of error, we utilize a deep learning algorithm to learn the complete and complex ADC behavior and to compensate for it in realtime. We demonstrate this "Deep ADC" technique on an 8G Sample/s 8-channel time-interleaved ADC with the QAM-OFDM modulated data. Simulation results for different QAM symbol constellations and OFDM subcarriers show dramatic improvements of approximately 5 bits in the dynamic range with a concomitant drastic reduction in symbol error rate. We further discuss the hardware implementation including latency, power consumption, memory requirements, and chip area.
用于无线通信的深度模数转换器
随着5G无线网络的出现,实现每秒数十千兆比特的吞吐量和低至几毫秒的延迟已经成为现实。这种性能水平将推动许多实时应用程序,例如自治和增强现实,在这些应用程序中,计算繁重的任务可以在云中执行。带宽的增加以及密集星座的使用给模数转换器(ADC)的速度和精度带来了巨大的负担。创建宽带adc的一种流行方法是利用多个通道,每个通道以时间交错的方式以较低的速度运行。然而,交错ADC有其自身的一系列挑战。并行架构对通道间失配、时序抖动、不同ADC通道之间的时钟倾斜以及单个通道内的非线性非常敏感。因此,需要在ADC之后使用数字信号处理(DSP)进行复杂的后校正。传统的DSP校准消耗大量的功率,其设计需要了解误差的来源和类型,这些误差在纳米CMOS工艺中变得越来越难以预测。在本文中,我们不是单独针对每个误差源,而是利用深度学习算法来学习完整而复杂的ADC行为并实时补偿它。我们在QAM-OFDM调制数据的8G采样/s 8通道时间交错ADC上演示了这种“深度ADC”技术。对不同QAM符号星座和OFDM子载波的仿真结果表明,在动态范围内显著提高了约5位,同时显著降低了符号错误率。我们进一步讨论硬件实现,包括延迟、功耗、内存需求和芯片面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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