Fibonacci Series Based Transition Reduction Dynamic Sector CODEC Design

Abstract

The process of data word transmission on an on-chip bus leads to switching activity of data bits on the bus wires, which charges and discharges the capacitance associated with the wires and consequently leads to dynamic power dissipation and delay increases. The amount of power dissipation at buses is significant compared to remaining circuit power dissipation. It is desirable to encode the values sent over these buses to decrease the switching activity and thereby reducing the bus power consumption and reducing the delay. In this paper, we present the input as Fibonacci sequence and partition the source word space into a number of sectors with a unique identifier. The combination of Fibonacci series and dynamic sector encoding technique (FS-DS) to reduce the number of transitions as well as to reduce the power dissipation and delay.