A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, J. Fox, K. Gharibdoust, Davide Gorret, A. Gupta, Christopher Hall, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, S. Raparthy, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
{"title":"A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET","authors":"A. Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, J. Fox, K. Gharibdoust, Davide Gorret, A. Gupta, Christopher Hall, A. Hassanin, Klaas L. Hofstra, Brian Holden, A. Hormati, J. Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, S. Raparthy, A. Shokrollahi, David Stauffer, Richard Simpson, A. Stewart, G. Surace, O. Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh","doi":"10.23919/VLSIC.2019.8778172","DOIUrl":null,"url":null,"abstract":"A 1.02pJ/b USR link carrying 416.67 Gb/s/mm die edge (500Gb/s aggregated data rate) in 16nm FinFET, while occupying 2.4mm2, is presented. To enable dense routing over conventional package material, a modified correlated NRZ signaling with low sensitivity to ISI, Xtalk, and common-mod noise has been developed. A matched CTLE/slicer topology has been employed to enhance robustness of the receiver over PVT. A very wideband Rx PLL tracks the majority of Tx jitter, resulting in significant power saving by relaxing Tx design constraints.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"33 1","pages":"C92-C93"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778172","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A 1.02pJ/b USR link carrying 416.67 Gb/s/mm die edge (500Gb/s aggregated data rate) in 16nm FinFET, while occupying 2.4mm2, is presented. To enable dense routing over conventional package material, a modified correlated NRZ signaling with low sensitivity to ISI, Xtalk, and common-mod noise has been developed. A matched CTLE/slicer topology has been employed to enhance robustness of the receiver over PVT. A very wideband Rx PLL tracks the majority of Tx jitter, resulting in significant power saving by relaxing Tx design constraints.
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