A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating

Abstract

The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signal-to-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 87% logic utilization that is significantly higher than a fully parallel binary LDPC decoder [7]. To achieve high energy efficiency, each processing node detects its own convergence and applies dynamic clock gating, and the decoder terminates when all nodes are clock gated. The dynamic clock gating and termination reduce the energy consumption by 62% for energy efficiency of 3.37nJ/b, or 277pJ/b/iteration, at a 1V supply.