A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align

Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao
{"title":"A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align","authors":"Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao","doi":"10.1109/ICICM54364.2021.9660276","DOIUrl":null,"url":null,"abstract":"An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"50 1","pages":"171-174"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM54364.2021.9660276","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.
基于快速时钟门控和tdac自对准的DDR4 SDRAM数据眼宽改善和ODT PVT容差增强
提出了一种具有快速时钟门控和ODT路径自对准技术的8Gb3200Mbps DDR4 SDRAM。在DDR4 SDRAM中使用快速时钟门控来追求减少DLL,读,写和ODT路径阶段,从而可以减少数据抖动和电流消耗。针对DDR4 SDRAM,提出了ODT路径延迟自对准方法,并在DRAM过程中实现。测试结果表明,快速时钟门控可以减少DLL、读、写和ODT通路的12级,减少600uA电流,减少5.4%的读和ODT通路抖动。此外,测量结果还表明,采用延迟自对准技术后,ttac变化从220ps降低到30ps。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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