2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices

Abstract

We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm node with cell heights of 100~110 nm and 30 nm gate pitch. Holistic analysis of the RO (Ring Oscillator) behavior, including MOL parasitics, all major variability sources, and stress proximity effects suggests that different FinFET and nanoslab transistor design options exhibit a wide range of power and performance differences. The key to improve FinFET PPA is to avoid fin cuts to maintain strong PMOS performance, and a key to improve SS corner delay is to use nanoslabs with tighter variability control.