The semantics of transactions and weak memory in x86, Power, ARM, and C++

Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2017-10-13 DOI:10.1145/3192366.3192373

Nathan Chong, Tyler Sorensen, John Wickerson

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引用次数: 26

Abstract

Weak memory models provide a complex, system-centric semantics for concurrent programs, while transactional memory (TM) provides a simpler, programmer-centric semantics. Both have been studied in detail, but their combined semantics is not well understood. This is problematic because such widely-used architectures and languages as x86, Power, and C++ all support TM, and all have weak memory models. Our work aims to clarify the interplay between weak memory and TM by extending existing axiomatic weak memory models (x86, Power, ARMv8, and C++) with new rules for TM. Our formal models are backed by automated tooling that enables (1) the synthesis of tests for validating our models against existing implementations and (2) the model-checking of TM-related transformations, such as lock elision and compiling C++ transactions to hardware. A key finding is that a proposed TM extension to ARMv8 currently being considered within ARM Research is incompatible with lock elision without sacrificing portability or performance.

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x86、Power、ARM和c++中事务和弱内存的语义

弱内存模型为并发程序提供了复杂的、以系统为中心的语义，而事务内存(TM)提供了更简单的、以程序员为中心的语义。两者都被详细研究过，但是它们的综合语义还没有被很好地理解。这是有问题的，因为诸如x86、Power和c++等广泛使用的体系结构和语言都支持TM，并且都具有较弱的内存模型。我们的工作旨在通过用新的TM规则扩展现有的公理弱内存模型(x86、Power、ARMv8和c++)来阐明弱内存和TM之间的相互作用。我们的正式模型由自动化工具支持，它支持(1)针对现有实现验证我们的模型的综合测试，以及(2)tm相关转换的模型检查，例如锁省略和编译c++事务到硬件。一个重要的发现是，ARM研究院目前正在考虑的ARMv8的TM扩展与锁省略不兼容，但不会牺牲可移植性或性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation

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