A Cartesian feedback-feedforward transmitter IC in 130nm CMOS

Abstract

A transmitter architecture based on Cartesian feedback-feedforward is described. A Cartesian feedback loop is used to linearize a transmitter and PA, and the error signal is utilized in a feedforward path to further enhance linearity. A proof-of-concept prototype transmitter IC that is used to linearize an external PA is demonstrated in a 130nm CMOS process. The implementation allows for a 8.7 dB ACLR improvement, compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16 QAM LTE signal with 1.4 MHz bandwidth.