A low minimum detectable power, high dynamic range, V-Band CMOS millimeter-wave logarithmic power detector

Abstract

This paper presents a V-Band logarithmic power detector fabricated in 90-nm CMOS technology. The topology of successive detection logarithmic amplifier (SDLA) is adopted for high dynamic range. Instead of using traditional differential limiting amplifiers, millimeter-wave (MMW) amplifiers are applied for the gain cells to achieve the desired performance. A three-stage SDLA test key was implemented. The measured results at 52 GHz show that the dynamic range is 50 dB and the logarithmic errors are within ±1.5 dB. From 50 to 62 GHz, the dynamic range is better than 35 dB, and the logarithmic errors are within ±2 dB. The total power consumption and chip size are 20 mW and 0.66 mm2, respectively. Compared to the previously reported millimeter-wave (MMW) power detectors, the proposed work features a wider dynamic range and reasonably linear logarithmic curve response to RF input power.