A low minimum detectable power, high dynamic range, V-Band CMOS millimeter-wave logarithmic power detector

C. Chou, Wen-Chian Lai, Tzuen-Hsi Huang, H. Chuang
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引用次数: 3

Abstract

This paper presents a V-Band logarithmic power detector fabricated in 90-nm CMOS technology. The topology of successive detection logarithmic amplifier (SDLA) is adopted for high dynamic range. Instead of using traditional differential limiting amplifiers, millimeter-wave (MMW) amplifiers are applied for the gain cells to achieve the desired performance. A three-stage SDLA test key was implemented. The measured results at 52 GHz show that the dynamic range is 50 dB and the logarithmic errors are within ±1.5 dB. From 50 to 62 GHz, the dynamic range is better than 35 dB, and the logarithmic errors are within ±2 dB. The total power consumption and chip size are 20 mW and 0.66 mm2, respectively. Compared to the previously reported millimeter-wave (MMW) power detectors, the proposed work features a wider dynamic range and reasonably linear logarithmic curve response to RF input power.
低最小可探测功率,高动态范围,v波段CMOS毫米波对数功率检测器
本文介绍了一种采用90纳米CMOS技术制作的v波段对数功率探测器。采用连续检测对数放大器(SDLA)拓扑结构实现高动态范围。增益单元采用毫米波(MMW)放大器代替传统的差分限制放大器,以达到预期的性能。实现了三阶段SDLA测试密钥。52 GHz频段的测量结果表明,动态范围为50 dB,对数误差在±1.5 dB以内。在50 ~ 62 GHz范围内,动态范围优于35 dB,对数误差在±2 dB以内。总功耗和芯片尺寸分别为20 mW和0.66 mm2。与先前报道的毫米波(MMW)功率探测器相比,该工作具有更宽的动态范围和对射频输入功率的合理线性对数曲线响应。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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