A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

Abstract

The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requirement in subsequent stages. However, these amplifiers generally induce issues such as large power consumption, stringent linearity requirements, and PVT-sensitive gain errors [1], [4]. Moreover, reduced voltage dynamic range in deep submicron nodes presents challenges for the design of high-performance amplifiers and fine quantizers in voltage domain. Therefore, implementing the fine quantizer in time domain becomes attractive due to its better noise tolerance and lower power consumption. Nevertheless, the linearity and conversion speed of the time-to-digital converter (TDC) used as the fine quantizer degrades quickly with the increase of its resolution due to the exponentially increased hardware. Moreover, its full-scale and resolution are determined by the delay cells and are thus sensitive to PVT variations. In prior-art, the time-domain assisted SAR ADC [2] adopts a current-discharging-based inner-tracking technique in a voltage-to-time converter (VTC) and TDC to compensate PVT variations, yet the conversion speed is limited by slow conversions of the VTC and the TDC. The digital slope assisted SAR ADC [3] guarantees that the time full-scale is aligned with the LSB in the voltage-domain. However, the architecture doesn't fully exploit the benefits of time-domain conversion since the ADC resolution is still dependent on the unit-capacitor switching, leading to an enlarged MSB-to-LSB ratio in the CDAC