Chunmei Wang, K. Chui, Xiangy-Yu Wang, T. Lim, Mingbin Yu, Gilbert See, G. Yu
{"title":"Passive Devices Fabrication on FOWLP and Characterization for RF Applications","authors":"Chunmei Wang, K. Chui, Xiangy-Yu Wang, T. Lim, Mingbin Yu, Gilbert See, G. Yu","doi":"10.1109/ECTC.2017.315","DOIUrl":null,"url":null,"abstract":"This paper presents the demonstration of integrated passive devices on a 300mm mold-first FOWLP technology platform with 3 metal layers (Cu RDL) build-up. In this case, a low-temperature cure, negative-tone polyimide (PI) material is selected as the inter-layer dielectric. MIM capacitors were fabricated on top of M1 RDL layer with low temperature CVD deposited inorganic as the dielectric and typical RDL barrier metal as the top and bottom electrode. Resistors were formed after M1 RDL layer by using typical RDL barrier metal as the thin film resistor. Last but not least, inductors were built on M2 RDL layer over epoxy mold material. Test keys for MIM capacitors, resistors and inductors were designed for electrical and RF characterization at the M2 layer.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"312-318"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2017.315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the demonstration of integrated passive devices on a 300mm mold-first FOWLP technology platform with 3 metal layers (Cu RDL) build-up. In this case, a low-temperature cure, negative-tone polyimide (PI) material is selected as the inter-layer dielectric. MIM capacitors were fabricated on top of M1 RDL layer with low temperature CVD deposited inorganic as the dielectric and typical RDL barrier metal as the top and bottom electrode. Resistors were formed after M1 RDL layer by using typical RDL barrier metal as the thin film resistor. Last but not least, inductors were built on M2 RDL layer over epoxy mold material. Test keys for MIM capacitors, resistors and inductors were designed for electrical and RF characterization at the M2 layer.