Perceptron Algorithm and Its Verilog Design

Abstract

In artificial neural network (ANN), the basic perceptron algorithm plays a significant role in supervised machine learning due to its simple structure. Though it cannot solve some non-linear problems like XOR, however, this feature offers a possibility to build perceptron on a hardware design. Due to high efficiency and defect tolerant, researchers have proposed some ANN accelerators with complicated memory units and specific registers. In this work, we focus on a simplest perceptron and accomplish its hardware design using Verilog HDL. The design module includes one core for learning and four memory units for storing the training data. The study shows that the proximate floating -point simulation of the simple perceptron design can replace the defect-tolerant registers and the simple memory units, thus to make the accelerator a tiny scale, it also demonstrates that the accuracy rate on test set achieved at 98% and the total area cost is only 0.0078 mm2.