Optimization of Wet strip after Metal Hard Mask All-in-One Etch for metal void reduction and yield improvement

Abstract

As semiconductor technology node continuously shrinks, Wet strip process works as a more important role beyond 45m. For RC delay concern, Ultra Low-K material is introduced to BEOL ILD (Interlayer Dielectric). After Trench First Metal Hard Mask All-in-One Etch, ULK film sidewalls are exposed during Wet strip. Wet strip needs to take care of not only no ULK K value shift, but also HM TiN pull back / remove for better gap fill capability. We systematically study Wet strip process parameters, clean efficiency is evaluated by metal void defect by defect scan after Cu CMP step. Device electrical test like Kevin-Via resistance and Via-Chain resistance are compared between old and optimized conditions. By optimization of Wet strip, remarkable metal void defect density is reduced and 20% yield improvement is achieved when device reliability is qualified.