Multilayer high-tc superconductor sampler circuit

Abstract

We designed and measured a high-Tc superconductor sampler circuit based on ramp-edge junctions with an upper-layer groundplane. Undesirable current distributions as a result of parasitic inductance occurred in the circuit. We experimentally observed that about 30% of signal and feedback current distributed to the control line of the read-out SQUID. During sampler operation, we avoided the effect of distributed current by selecting a suitable detection timing for output voltage and we successfully measured a signal current waveform using the circuit at 50 K.